A computing system may be built to accommodate a variety of CPU speeds. Changes in CPU speed may result simply from the availability of CPU's that can be driven at higher clock speeds. Changes in CPU speed can also occur when a system has a power-saving mode that involves decreasing clock speed or when a user has an upgradable system and installs a faster CPU. In such cases, the system designer may have designed portions of the system to deal with the higher clock speed, but the timing requirements for at least some peripheral devices and for memory may remain the same. In an extreme case, the new timing relationship of CPU and peripheral device or memory results in incompatibility. More often, the change in speed causes a less than optimum relationship between the CPU and peripheral devices or memory.
In many systems the CPU speed is configured by selection of a switch or jumper (or a combination of switches and jumpers). The outputs of these switches are typically applied to the input of a frequency synthesizer, which in turn generates the desired CPU clock frequency signal based on the state of its inputs. It is possible to program a CPU to sense its own dock speed, but this procedure differs for CPUs from different manufacturers and often proves to be inaccurate. Even if the CPU were able to sense its own clock speed, there remains the issue of what steps the CPU could take to utilize the information to adjust the timing of its communications with peripheral devices or memory. Such adjustment may necessitate replacing the state machines controlling those devices.
What is needed is a method for adapting a system to accommodate changes in CPU speeds, to reduce disruptions in communications between the CPU and peripheral devices or memory.